AI Model Performance and Hardware Optimization Explained
Explore AI model performance and hardware optimization, focusing on KV cache, memory, and serving runtime for efficient inference.
The model is waiting on memory
A long chatbot conversation can look smooth on screen, one token appearing after another. Inside the server, every new token forces the model to consult the history it has already processed.
That history is held in the KV cache, short for key-value cache. It is the persistent attention state left behind when a transformer model processes prior tokens, and it increasingly determines decode speed.
IBM Technology describes the cache as the model’s notebook. Each token leaves keys and values at every attention layer, so the next token can reuse earlier work instead of recalculating it.
Without that reuse, generation would repeatedly rebuild attention information for the whole conversation. With it, the model still performs fresh computation for each output token, but it avoids recreating the historical attention state.
The catch is size. Every extra token in the prompt or generated answer expands the KV cache, and every active user request needs its own cache state. Long context windows turn memory capacity into a first-order serving constraint.
For a team running a coding assistant, this is visible as a familiar failure mode: the model can handle several short tasks quickly, then throughput falls when users leave long repositories, terminal logs, and chat histories attached.
Why the same model runs differently on different chips
The key hardware problem is a mismatch between where the cache fits and where computation runs fastest. Large memory can hold the cache, while smaller local memory can feed compute units at much higher speed.
IBM Technology’s comparison starts with GPUs. In a typical data center GPU setup, KV-cache blocks reside in high-bandwidth memory, or HBM, on the device. On-chip memory and caches serve the compute units.
A serving runtime such as vLLM allocates cache blocks on demand instead of reserving one large contiguous region for every request. It tracks those blocks through an address table, much like virtual memory management in an operating system.
The runtime therefore helps determine whether a server keeps working efficiently as requests arrive, end, and vary in length. The attention kernel then determines how cache data is read and assembled through on-chip memory.
GPUs are not passive in this process. Their memory system, caches, and compute hardware matter, but the runtime and kernels decide how requests are packed, where cache blocks go, and which memory accesses occur during attention.
Google’s TPU architecture faces the same large-memory versus fast-local-memory tension, but hands more orchestration to the compiler. KV state sits in HBM, while computation runs from a faster on-chip store called vector memory, or VMEM.
The compiler cuts the work into tiles and schedules a pipeline. While the accelerator computes on one tile, hardware copy engines can fetch the next tile, aiming to avoid leaving compute units idle while they wait for data.
IBM’s Spyre accelerator makes this software control more explicit. Each card has 128 GB of LPDDR5 memory and 32 active cores, while each core has a 2 MB programmable SRAM scratchpad managed through compiler-scheduled loads and stores.
That explicit scratchpad design gives compiler tooling greater responsibility. It must partition attention work and move the right cache data into the 2 MB local store at the right time, instead of relying on conventional automatic hardware caching.
These designs can run the same transformer weights and generate different tokens-per-second results. The difference may come from memory capacity, bandwidth, cache locality, compiler scheduling, kernel behavior, or the serving runtime’s allocation policy.
Dell also describes inference infrastructure moving toward multi-tier memory systems that manage several classes of model state, rather than treating every KV-cache entry as identical [5]. That direction reflects the cost of storing every token at the fastest tier.
KV cache is capacity, bandwidth, and scheduling
KV-cache optimization is often presented as a memory-capacity problem. It is also a data-movement problem. A server can have enough memory to hold an enormous cache and still generate slowly if attention repeatedly pulls data inefficiently.
A short prompt and one active request can keep much of the working set close to compute. A long context and many simultaneous requests force the system to retrieve more state from larger, slower memory layers.
This explains why peak FLOPS is an incomplete buying metric for inference. FLOPS estimates how much math a chip can theoretically execute, while decoding often depends on how quickly it can retrieve and reuse existing attention state.
More memory helps, but it has costs. Tesla’s announced SI5 accelerator targets 96 GB of memory to support larger workloads, including bigger KV caches [4]. Extra capacity can support longer contexts or higher concurrency, not automatically lower latency.
Compression offers another route, with its own engineering risk. Google’s TurboQuant work, as reported by Tom’s Hardware, compresses KV-cache values to three bits, claiming a sixfold memory reduction and up to an eightfold speedup in attention-logit computation on NVIDIA H100 GPUs [4].
Those figures describe a particular method and hardware setup, not a universal serving result. Compression changes the numerical representation of model state, so you need quality evaluation on your prompts, model, quantization scheme, and context lengths.
We would begin with cache measurements: average prompt length, average generated length, concurrent requests, cache hit behavior, and time spent in decode. A new accelerator is expensive if fragmented allocation or unoptimized attention kernels are the bottleneck.
A chip-design lab’s model result is also a systems result
Recursive, a chip-design-focused lab founded by people associated with Google’s AlphaChip work, released Ripple 65B-Preview, a 65-billion-parameter dense open-weight language model. The lab’s broader pitch is to use AI to design chips, then use improved chips to train AI.
Sam Witteveen reports that Recursive said Ripple scored 80.52 on Terminal Bench 2.1, above Reflection’s reported 80.1 for its 500-billion-parameter Beam model and Meta’s reported 76.4 for the 816-billion-parameter Muse Spark Open model.
The headline needs its qualifiers. Recursive framed Ripple as the leading US open-weight model on that benchmark, while Witteveen notes reported scores for Chinese open models, including DeepSeek Flash 4.1, Xiaomi MiMo 2.6 Pro, Kimi K3, and GLM 5.3, were higher.
Ripple’s 65 billion parameters also do not mean it is tiny. It is a dense model, meaning its full parameter set participates in each token prediction, unlike a mixture-of-experts model that activates only a subset of specialized parameter groups.
Recursive chose density over mixture-of-experts complexity. Witteveen says the lab reported about 40 percent model FLOPs utilization during training and post-training, while avoiding custom kernels and quantization in its reported training setup.
Dense models can be easier to train and serve, but the entire weight set must remain available for each generated token. Mixture-of-experts designs can reduce active compute per token, while increasing routing, storage, and systems complexity.
Ripple was pretrained on 12 trillion tokens, supports up to one million tokens of context, and has an Apache 2.0 license, according to Witteveen. Recursive also released a base model, an instruction-tuned version, and bfloat16 and NVFP4 variants.
The base-model release matters if you need to fine-tune or post-train for internal code, tools, or policies. Many open-weight releases expose only an instruction-tuned checkpoint, which limits what you can change upstream of the chat behavior.
Benchmark scores depend on the harness
Terminal Bench measures an agent performing terminal-based tasks, not static code completion. A model must use tools, observe outcomes, maintain task state, and decide what to do over multiple steps.
That makes the agent harness part of the measured system. Witteveen notes that vendor-reported Terminal Bench results may use different harnesses, and independent runs from VALS produced lower scores for several models than their vendors reported.
AgentFloor reaches a related result from a broader set of tool-use tasks. Its authors ran 16,542 evaluations across 16 open-weight models and GPT-5, finding smaller models could handle short-horizon tasks while frontier models were stronger on longer-horizon planning [1].
For deployment, a narrow score gap may matter less than your runtime costs, licensing requirements, local hardware, context needs, and tool reliability. A model that performs well with one harness can behave differently with your shell, permissions, repository, and failure recovery.
Recursive said Ripple’s full research-and-development effort cost $32 million, including experiments, data work, evaluations, and post-training, according to Sam Witteveen. That is broader than the cost of one final pretraining run, but it remains the lab’s own reported accounting.
Outside estimates for model training vary sharply because hardware ownership, cloud pricing, staffing, data preparation, and failed experiments change the total. ComputeStacker and Capital & Compute both present estimates rather than a verified cost breakdown for a specific 65-billion-parameter run [2][3].
The more interesting part of Recursive’s release is its method. The lab used a sequence of smaller models, described as a training ladder built from AI2’s OLMo 3 work, to test architectural changes before committing to large-scale training.
Witteveen says Recursive discarded variants that looked promising at small scale but did not retain gains around four billion parameters and above. That is disciplined experimental design, not evidence of one hidden architectural breakthrough.
Its post-training pipeline reportedly built synthetic data and environments internally, then increased task difficulty as the model improved. Recursive reported reaching its Terminal Bench result with 1.4 million reinforcement-learning rollouts.
Model editing and hardware solve different bottlenecks
MIT work highlighted by Two Minute Papers points at a different kind of performance improvement: editing model weights. The experiments had OpenAI’s GPT-6 Astra inspect other neural-network weights and identify behaviors encoded in those parameters.
In one reported experiment, Astra identified simplified games that an examined network had been trained to play. In another, it edited a driving network’s weights so the vehicle succeeded on a ramp where it had previously become stuck.
The most striking language-model result involved Qwen, an open-weight model family. Two Minute Papers reports a math benchmark score rising from about 8 percent to about 48 percent after an edit intended to suppress repetitive reasoning loops.
That does not mean the edit taught Qwen mathematics from scratch. The reported interpretation is narrower: the model already had relevant capability, but its behavior was being obstructed by a looping failure pattern.
It also does not mean automated model surgery reliably improves all systems. The channel reports that Astra did not achieve meaningful improvements on Gemma 3, and that the reading, fixing, and improving demonstrations used separate, mostly small-model experiments.
For builders, this is the boundary to keep straight. Weight editing can change what a model does, while KV-cache management changes how efficiently hardware serves what the model already does. Both can move an end-to-end benchmark, through different mechanisms.
Frequently Asked Questions
How does KV cache affect AI model inference speed?
KV cache stores the attention state from previous tokens, allowing the model to reuse prior computations instead of recalculating them. This reuse speeds up token generation but the cache size grows with longer contexts and more active requests, which can increase memory pressure and slow down decoding. Efficient KV cache management is therefore critical to maintaining inference speed.
Why do AI models perform differently on various hardware?
Performance differences arise because hardware varies in how it balances memory capacity, bandwidth, and compute speed. For example, GPUs store KV cache in high-bandwidth memory while running computation on faster on-chip caches. Differences in memory hierarchy, compiler scheduling, kernel design, and serving runtime policies all affect how efficiently the model processes tokens, leading to varied tokens-per-second rates.
What hardware factors impact transformer model decoding latency?
Decoding latency depends on memory capacity to hold the KV cache, memory bandwidth to move data efficiently, and the locality of cache data relative to compute units. On-chip memory speed and how well the serving runtime schedules data movement also influence latency. Larger caches and many simultaneous requests can increase retrieval times from slower memory tiers, raising latency.
How can memory bandwidth and capacity optimize AI model serving?
Sufficient memory capacity allows longer contexts and more concurrent requests, while high memory bandwidth ensures quick data movement for attention computations. However, simply increasing capacity does not guarantee lower latency; efficient scheduling and cache locality are also necessary. Compression techniques can reduce memory use and speed up operations but require careful quality evaluation.
What role does the serving runtime play in AI model performance?
The serving runtime manages KV cache allocation and request scheduling, deciding how cache blocks are assigned and accessed. It influences system efficiency as requests vary in length and concurrency, affecting how well the hardware resources are utilized. The runtime works alongside kernels and compilers to optimize memory access patterns and maintain throughput.
How we researched this
This article was assembled from 3 video sources across 3 channels, 8 cited references.
Nothing here is based on hands-on testing. Where a figure or finding appears, it belongs to the source cited beside it, and the writing says so rather than implying otherwise. Every source is listed below so you can check it.
Sources
The OpenAI Astra Weight Hack, Explained, Two Minute Papers
Ripple 65B: A Chip Design Lab Just Beat Every US Open Model, Sam Witteveen
Why AI Models Run Faster on Some Chips: The KV Cache Effect, IBM Technology
AgentFloor: How Far Up the tool use Ladder Can Small Open-Weight Models Go?
Tesla unveils AI accelerator roadmap, adopts new 'SI' branding in 'Super Intelligence' push
RLE-Bench: A Qualifying Exam for Coding Agents as Robot Learning Engineers
Watch AI Model Performance and Hardware Optimization on Youtube
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